As fiber optic data transmission speeds increase, higher linearity will be needed from physical media dependent (PMD) Integrated Circuits (ICs) such as transimpedance amplifiers, modulators and/or laser drivers. In particular, higher linearity transimpedance amplifiers will be needed to support higher order modulation schemes such as differential phase-shift keying (DPSK) or binary phase-shift keying (BPSK), electronic dispersion compensation (EDC), and burst mode data transmission systems.
One conventional solution for implementing a wide dynamic range transimpedance amplifier uses a DC restore topology for linearizing a single-ended pre-amplifier stage of a multi-stage transimpedance amplifier. In addition, the transimpedance amplifier offset correction under power drive (which does not use feedback), enables such correction to be applied to a 40 Gigabit per second (Gbs) burst-mode transimpedance amplifier. However, such an implementation has room for overall linearity improvement.
Conventional approaches for linearizing the second stage of a transimpedance amplifier often implement a differential limiter amplifier. Such an implementation typically has used some sort of signal detection near the output of the transimpedance amplifier that is fed back to an intermediate stage configured for automatic gain control.
A differential limiter amplifier also allows the integration of a differential offset correction using a common detection circuit. However, because the detection is done near the output, significant distortion of the signal occurs before the automatic gain control loop can effectively reduce the signal to reduce the distortion. This may lead to residual or multiplicative distortion. In addition, feedback automatic gain control is not conducive of high performing burst-mode transimpedance amplifier operation due to the delay in the feedback signal.
Referring to FIG. 1, a block diagram of a conventional transimpedance amplifier is shown. Typically a multi-stage transimpedance amplifier designed for 40 Gbs is fabricated in high speed SiGe, CMOS, InP HBT, or PHEMT technologies. Most implementations use three stages to obtain the desired high transimpedance gain. The three stages include a transimpedance amplifier preamplifier followed by a differential VGA (or post or limiting) amplifier. The differential amplifier section connects to an output buffer stage to interface with a 50 ohm system. When implementing a design in silicon technologies, the first stage is usually a differential amplifier due to the lack of backside vias or good single-ended grounds. When implementing a design in InP or GaAs HBTs or PHEMTs, the first stage is normally single-ended and will use a DC restore loop to linearize the input stage.
For a silicon differential input transimpedance amplifier preamplifier employment, a DC compensation loop is usually fed back to the unused differential input, similar to what is depicted for the VGA stage in FIG. 1, but wrapped all the way to a preceding differential input preamplifier stage. In most conventional approaches, the DC compensation loop shown in FIG. 1 will be implemented where a signal is detected at the output buffer stage (or a stage close to the output so a significant signal is detected). The DC compensation loop will be fed back to the un-driven port of a preceding differential amplifier VGA stage which is driven single-endedly. Such a loop corrects the output offset created from driving only one input of a VGA stage. Such a loop improves duty cycle distortion caused by imbalanced excitation of the VGA stage.
In order to linearize the operation of the VGA stage (assuming the transimpedance amplifier preamplifier output has already been linearized in the case of a preceding single-ended transimpedance amplifier), a signal level is usually also detected at or near the output buffer stage and is fed back to an automatic gain control port of a VGA amplifier stage that has gain control capability.
It would be desirable to enhance the linearity of the second stage of a transimpedance amplifier to support DPSK modulation and/or electronic dispersion compensation (EDC) applications in a manner that may also be compatible with burst-mode operation.